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CAT130xx
Voltage Supervisor with Microwire Serial CMOS EEPROM
FEATURES
Precision Power Supply Voltage Monitor 5V, 3.3V, 3V & 2.5V systems 7 threshold voltage options Active High or Low Reset Valid reset guaranteed at VCC = 1 V High Speed Operation Selectable x8 or x16 memory organization Low power CMOS technology 1,000,000 Program/Erase cycles 100 year data retention Industrial temperature range RoHS-compliant 8-pin SOIC package For Ordering Information details, see page 13.
DESCRIPTION
The CAT130xx (see table below) are memory and supervisory solutions for microcontroller based systems. A CMOS serial EEPROM memory and a system power supervisor with brown-out protection are integrated together. Memory interface is via Microwire serial protocol. The CAT130xx provides a precision VCC sense circuit with two reset output options: CMOS active low output or CMOS active high. The RESET output is active whenever VCC is below the reset threshold or falls below the reset threshold voltage. The power supply monitor and reset circuit protect system controllers during power up/down and against brownout conditions. Seven reset threshold voltages support 5V, 3.3V, 3V and 2.5V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 240ms after the supply voltage exceeds the reset threshold level.
PIN CONFIGURATION
SOIC (W)
CS SK DI DO 1 2 3 4 8 VCC 7 RST/ RST 6 ORG 5 GND
MEMORY SIZE SELECTOR
Product 13001 13004 13008 13016 Memory density 1-Kbit 4-Kbit 8-Kbit 16-Kbit
PIN FUNCTION
Pin Name CS SK DI DO GND ORG RST/ RST VCC Function Chip Select Clock Input Serial Data Input Serial Data Output Ground Memory Organization Reset Output Power Supply
THRESHOLD SUFFIX SELECTOR
Nominal Threshold Voltage 4.63V 4.38V 4.00V 3.08V 2.93V 2.63V 2.32V Threshold Suffix Designation L M J T S R Z
Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization.
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Doc. No. MD-1121 Rev. B
CAT130xx BLOCK DIAGRAM
VCC
DO ORG CS SK DI EEPROM VOLTAGE DETECTOR RST or RST
VSS
ABSOLUTE MAXIMUM RATINGS(1) Parameters Storage Temperature Voltage on Any Pin with Respect to Ground RELIABILITY CHARACTERISTICS(3) Symbol NEND
(4) (2)
Ratings -65 to +150 -0.5 to +6.5
Units C V
Parameter Endurance Data Retention
Min 1,000,000 100
Units Program/ Erase Cycles Years
TDR
D.C. OPERATING CHARACTERISTICS VCC = +2.5V to +5.5V unless otherwise specified. Symbol ICC ISB IL VIL VIH VOL VOH Parameter Supply Current Standby Current I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 -0.5 2.0 12 10 Min. Limits Typ. Max. 3 25 20 2 0.8 VCC + 0.5 0.4 VCC 2.5V, IOL = 2.1mA VCC 4.5V, IOH = -0.4mA Test Condition Read or Write at 1MHz VCC < 5.5V; All I/O Pins at VSS or VCC VCC < 3.6V; All I/O Pins at VSS or VCC Pin at GND or VCC Units mA A A V V V V
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Block Mode, VCC = 5 V, 25C
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CAT130xx
A.C. CHARACTERISTICS (MEMORY)(1) VCC = +2.5V to 5.5V, TA = -40C to 85C, unless otherwise specified. Symbol fSK tCSS tCSH tCSMIN tSKHI tSKLOW tDIS tDIH tPD1 tPD0
(1) tHZ
Parameter Clock Frequency CS Setup Time CS Hold Time Minimum CS Low Time Minimum SK High Time Minimum SK Low Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Status Valid Program/Erase Pulse Width Power-up to Ready Mode
Min DC 50 0 0.25 0.25 0.25 100 100
Max 2000
Units kHz ns ns s s s ns ns
0.25 0.25 100 0.25 5 1
s s ns s ms ms
tSV tEW tPU
Notes: (1) (2) (3)
(2), (3)
Test conditions according to "A.C. Test Conditions" table. Tested initially and after a design or process change that affects this parameter. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS Input Rise and Fall Times Input Levels Input Levels Timing Reference Levels Timing Reference Levels Output Load 50 ns 0.4V to 2.4V (4.5V < VCC < 5.5V) 0.2VCC to 0.7VCC (2.5V < VCC < 4.5V) 0.8V, 2.0V (4.5V < VCC < 5.5V) 0.5VCC (2.5V < VCC < 4.5V) Current Source: IOL max / IOH max; CL = 100pF
(c) 2008 SCILLC. All rights reserved. Characteristics subject to change without notice
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Doc. No. MD-1121 Rev. B
CAT130xx
ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION) VCC = Full range, TA = -40C to +85C unless otherwise noted. Typical values at TA = +25C and VCC = 5V for L/M/J versions, VCC = 3.3V for T/S versions, VCC = 3V for R version and VCC = 2.5V for Z version. Symbol VTH Parameter Reset Threshold Voltage Threshold L M J T S R Z Conditions TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C Min 4.56 4.50 4.31 4.25 3.93 3.89 3.04 3.00 2.89 2.85 2.59 2.55 2.28 2.25 Min Typ(1) 30 VCC = VTH to (VTH -100mV) TA = -40C to +85C VCC = VTH min, ISINK = 1.2 mA R/S/T/Z VCC = VTH min, ISINK = 3.2 mA J/L/M VCC > 1.0V, ISINK = 50A VOH RESET Output Voltage High (Push-pull, active LOW, CAT130xx9) RESET Output Voltage Low VOL (Push-pull, active HIGH, CAT130xx1) RESET Output Voltage High VOH
Notes: (1) (2) Production testing done at TA = +25C; limits over temperature guaranteed by design only. RESET output for the CAT130xx9; RESET output for the CAT130xx1.
Typ 4.63 4.38 4.00 3.08 2.93 2.63 2.32
Max 4.70 4.75 4.45 4.50 4.06 4.10 3.11 3.15 2.96 3.00 2.66 2.70 2.35 2.38 Max
Units
V
Symbol Parameter Reset Threshold Tempco tRPD tPURST VCC to Reset Delay
(2)
Conditions
Units ppm/C s
20 140 240 460 0.3 0.4 0.3 0.8VCC
Reset Active Timeout Period RESET Output Voltage Low (Push-pull, active LOW, CAT130xx9)
ms
VOL
V
VCC = VTH max, ISOURCE = -500A R/S/T/Z VCC = VTH max, ISOURCE = -800A J/L/M VCC > VTH max, ISINK = 1.2mA R/S/T/Z VCC > VTH max, ISINK = 3.2mA J/L/M 1.8V < VCC VTH min, ISOURCE = -150A
V VCC - 1.5 0.3 V 0.4
(Push-pull, active HIGH, CAT130xx1)
0.8VCC
V
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(c) 2008 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT130xx PIN DESCRIPTION
RESET/RESET: The reset output is available in two versions: CMOS Active Low (CAT130xx9) and CMOS Active High (CAT130xx1). Both versions are push-pull outputs for high efficiency. DI: The serial data input pin accepts op-codes, addresses and data. The input data is latched on the rising edge of the SK clock input. DO: The serial data output pin is used to transfer data out of the device. The data is shifted out on the rising edge of the SK clock. SK: The serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and CAT130xx device. CS: The chip select input pin is used to enable/disable the CAT130xx. When CS is high, the device is selected and accepts op-codes, addresses and data. Upon receiving a Write or Erase instruction, the falling edge of CS will start the internal write cycle to the selected memory location. ORG: The memory organization input selects the memory configuration as either register of 16 bits (ORG tied to VCC or floating) or 8 bits (ORG connected to GND). RESET CONTROLLER DESCRIPTION The reset signal is asserted LOW for the CAT130xx9 and HIGH for the CAT130xx1 when the power supply voltage falls below the threshold trip voltage and remains asserted for at least 140ms (tPURST) after the power supply voltage has risen above the threshold. Reset output timing is shown in Figure 1. The CAT130xx devices protect Ps against brownout failure. Short duration VCC transients of 4sec or less and 100mV amplitude typically do not generate a Reset pulse. Figure 2 shows the maximum pulse duration of negative-going VCC transients that do not cause a reset condition. As the amplitude of the transient goes further below the threshold (increasing VTH - VCC), the maximum pulse duration decreases. In this test, the VCC starts from an initial voltage of 0.5V above the threshold and drops below it by the amplitude of the overdrive voltage (VTH - VCC).
TRANSIENT DURATION [s]
TAMB = 25C
CAT130xxZ
DEVICE OPERATION
The CAT130xx products combine the accurate voltage monitoring capabilities of a standalone voltage supervisor with the high quality and reliability of standard EEPROMs from Catalyst Semiconductor.
CAT130xxM
RESET OVERDRIVE V TH - VCC [mV]
Figure 2. Maximum Transient Duration without Causing a Reset Pulse vs. Overdrive Voltage
VTH VCC V RVALID t PURST t RPD t PURST
t RPD
RESE T
CAT130xx9
RESE T
CAT130xx1
Figure 1. RESET Output Timing
(c) 2008 SCILLC. All rights reserved. Characteristics subject to change without notice
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Doc. No. MD-1121 Rev. B
CAT130xx EMBEDDED EEPROM OPERATION
The CAT130xx has a nonvolatile embedded memory intended for use with industry standard micropro- cessors. The memory can be organized as either registers of 16 bits or 8 bits. The CAT130xx operates on a single power supply and will generate on chip the high voltage required during any write operation. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (13001) / 8-bit (13004) / 9-bit (13008) / 10-bit (13016) address (an additional bit when organized as x8) and for write operations a 16-bit data field (8-bit for x8 organization). The instruction format is shown in Instruction Set Table.
INSTRUCTION SET Instruction READ Device 13001 13004 13008 13016 13001 13004 13008 13016 13001 13004 13008 13016 13001 13004 13008 13016 13001 13004 13008 13016 13001 13004 13008 13016 13001 13004 13008 13016 Start Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Address Opcode 10 10 10 10 11 11 11 11 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 x8 A6-A0 A8-A0 A9-A0 A10-A0 A6-A0 A8-A0 A9-A0 A10-A0 A6-A0 A8-A0 A9-A0 A10-A0 11xxxxx 11xxxxxxx 11xxxxxxxx 11xxxxxxxxx 00xxxxx 00xxxxxxx 00xxxxxxxx 00xxxxxxxxx 10xxxxx 10xxxxxxx 10xxxxxxxx 10xxxxxxxxx 01xxxxx 01xxxxxxx 01xxxxxxxx 01xxxxxxxxx x 16 A5-A0 A7-A0 A8-A0 A9-A0 A5-A0 A7-A0 A8-A0 A9-A0 A5-A0 A7-A0 A8-A0 A9-A0 11xxxx 11xxxxxx 11xxxxxxx 11xxxxxxxx 00xxxx 00xxxxxx 00xxxxxxx 00xxxxxxxx 10xxxx 10xxxxxx 10xxxxxxx 10xxxxxxxx 01xxxx 01xxxxxx 01xxxxxxx 01xxxxxxxx x8 Data x 16 Comments Read Address AN-A0
ERASE
Clear Address AN-A0
WRITE
D7-D0 D7-D0 D7-D0 D7-D0
D15-D0 D15-D0 D15-D0 D15-D0
Write Address AN-A0
EWEN
Write Enable
EWDS
Write Disable
ERAL
Clear All Addresses
WRAL
D7-D0 D7-D0 D7-D0 D7-D0
D15-D0 D15-D0 D15-D0 D15-D0
Write All Addresses
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(c) 2008 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT130xx
Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status during a write operation. The serial communication protocol follows the timing shown in Figure 3. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy "1" into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The Ready/Busy flag can be disabled only in Ready state; no change is allowed in Busy state. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT130xx will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). The READ instruction timing is illustrated in Figure 4. For the CAT13004/08/16, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit.
Figure 3. Sychronous Data Timing
tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH
Figure 4. Read Instruction Timing
SK tCSMIN CS STANDBY AN DI 1 1 0 tHZ 0 DN DN-1 D1 D0 HIGH-Z AN-1 A0
DO
HIGH-Z
tPD0
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Doc. No. MD-1121 Rev. B
CAT130xx
Erase/Write Enable and Disable The CAT130xx powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT130xx write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. The EWEN and EWDS instructions timing is shown in Figure 5. Write After receiving a WRITE command (Figure 6), address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking for auto-clear and data store cycles on the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT130xx can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into.
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
* * ENABLE=11 DISABLE=00
Figure 6. Write Instruction Timing
SK tCSMIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY HIGH-Z tHZ AN-1 A0 DN D0 STATUS VERIFY STANDBY
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(c) 2008 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT130xx
Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN (Figure 7). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT130xx can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical "1" state. Figure 7. Erase Instruction Timing
SK
Erase All Upon receiving an ERAL command (Figure 8), the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT130xx can be determi- ned by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical "1" state.
CS AN DI 1 1 1 tSV HIGH-Z DO AN-1 A0
STATUS VERIFY tCS
STANDBY
tHZ BUSY tEW READY HIGH-Z
Figure 8. ERAL Instruction Timing
SK
CS
STATUS VERIFY tCS
STANDBY
DI
1
0
0
1
0 tSV tHZ BUSY tEW READY HIGH-Z
DO
HIGH-Z
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Doc. No. MD-1121 Rev. B
CAT130xx
Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (Figure 9). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode.
The ready/busy status of the CAT130xx can be deter- mined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed.
Figure 9. WRAL Instruction Timing
SK
CS
STATUS VERIFY tCSMIN
STANDBY
DI
1
0
0
0
1
DN
D0 tSV tHZ BUSY tEW READY HIGH-Z
DO
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(c) 2008 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT130xx PACKAGE OUTLINE DRAWING
8-LEAD 150 MIL SOIC (W)
E1 E
D
h x 45 C A q1
e b
A1 L
SYMBOL A1 A b C D E E1 e h L q1
MIN 0.10 1.35 0.33 0.19 4.80 5.80 3.80
NOM
MAX 0.25 1.75 0.51 0.25 5.00 6.20 4.00
1.27 BSC 0.25 0.40 0 0.50 1.27 8
Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC specification MS-012 dimensions.
(c) 2008 SCILLC. All rights reserved. Characteristics subject to change without notice
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Doc. No. MD-1121 Rev. B
CAT130xx PACKAGE MARKING
8-LEAD SOIC
130XXZWI
CSI XX Z I YY WW A 4
4YYWWA
= = = = = = = =
Catalyst Semiconductor, Inc. Device Code (see Marking Code table below) Supervisory Output Code (see Marking Code table below) Temperature Range Production Year Production Week Product Revision Lead Finish NiPdAu Device Marking Codes XX 13001 13004 13008 13016 01 04 08 16 Supervisory Marking Codes Z
Output Active Low Output Active High
9 1
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(c) 2008 SCILLC. All rights reserved. Characteristics subject to change without notice
CAT130xx EXAMPLE OF ORDERING INFORMATION
Prefix CAT Device # Suffix 13001 9 S W I G T3
Lead Finish G: NiPdAu (PPF) Company ID Temperature Range I = Industrial (-40C to 85C) Product Type with Memory Density 13001: 1-Kb EEPROM 13004: 4-Kb EEPROM 13008(5): 8-Kb EEPROM 13016(5): 16-Kb EEPROM Tape & Reel T: Tape & Reel 3: 3000 units / Reel
Package W: SOIC
Reset Threshold Voltage L: 4.50V - 4.75V M: 4.25V - 4.50V J: 3.89V - 4.10V T: 3.00V - 3.15V S: 2.85V - 3.00V R: 2.55V - 2.70V Z: 2.25V - 2.38V
Supervisor Output Type 9: CMOS Active Low 1: CMOS Active High
Notes: (1) (2) (3) (4) (5) All packages are RoHS-compliant (Lead-free, Halogen-free). The standard lead finish is NiPdAu pre-plated (PPF) lead frames. The device used in the above example is a CAT130019SWI-GT3 (1Kb EEPROM, with Active Low CMOS output, with a reset threshold between 2.85V - 3.00V, in an SOIC, Industrial Temperature, NiPdAu, Tape and Reel. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. For 8-Kb and 16-Kb embedded EEPROM option availability please contact your nearest ON Semiconductor Sales office.
(c) 2008 SCILLC. All rights reserved. Characteristics subject to change without notice
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Doc. No. MD-1121 Rev. B
CAT130xx REVISION HISTORY
Date 17-Jan-07 7-Nov-08 Rev. A B Description Initial Issue Change logo and fine print to ON Semiconductor
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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